What is TLB?

Overview

A specific cache used to maintain the record of recently used virtual to physical memory transactions is called a Translation Lookaside Buffer (TLB). It is comprised of page numbers and their corresponding frame numbers that is stored in each TLB entry. TLB can be accessed by using the virtual page numberIt is a component of logical address in TLB which helps in mapping frame numbers to corresponding physical addresses. For this cause, it is known as Address Translation Cache.

Importance

Paging supports a virtual memory mechanism, which impacts the page table read and delays every load and store operation at least twice. It demands a considerable amount of mapping data as it divides the process into pages, which are small, fixed-sized blocks. Since the mapping data is typically maintained in primary storage, paging necessitates an additional memory lookup for every virtual address the CPU generates. It would be prolonged to read transactional data from memory before every operation.

Note: Accessing the TLB takes less time than accessing the main memory because it is a memory cache close to the CPU.

Mechanism

If a virtual address is provided, then the CPU checks the TLB. If a page table entry is matched (TLB hit), then the frame number is accessed, and the physical address is generated. When processing a page table, if an entry is missing from the TLB (TLB miss), then first, the TLB determines whether the page is already present in primary storage; if not, a page fault is sent; and second, the TLB is reset to add the new page entry.

Requests are transmitted straight from the CPU to the cache when the cache is virtually addressed, and the TLB is only used when the cache is missed. The CPU performs a TLB lookup on each memory transaction if the cache is physically addressed and the resultant physical address is transferred to the cache.

Workflow of TLB

The workflow of TLB is defined as:

TLB hit steps

The following steps are involved in TLB hit case:

1. The CPU generates a virtual memory address.
2. If the page number exists in TLB, then the corresponding frame number and offset are retrieved, which is known as a physical address.
3. It checks the cache to ensure the presence of the particular data block; if data is presented, it is accessed. Otherwise, cache will be updated.

TLB miss steps

Likewise, TLB miss steps are as follows:

1. The CPU generates a virtual memory address.
2. If the page number does not present in TLB, then the corresponding page table is used for processing this request. If it is present in the page table, then go to step 3 of TLB Hit Steps.
3. If the corresponding page number is not in the page table, then search the secondary memory and transfer the data to the main memory.
4. If the memory is not fully filled, then update the page table and TLB, respectively.
5. If the memory is fully occupied, replacement techniques (LRU, FIFO, MRU) come into the picture that will aid in making space for the newly accessed page. Lastly, update the page table and TLB.

Working

The following illustrates the step-by-step procedure for TLB hit:

Similarly, the working of TLB miss is shown below:

Effective memory access time (EMAT)

EMAT is calculated with the help of the following formula:

$EMAT = h(c+m) + (1-h)(c+2m)$

Where $h$ is TLB hit ratio, $m$ is the memory access time, and $c$ is TLB access time.

Note: This formula is only valid when single-level paging is in use, and there are no page faults.

Advantages

• TLB hit rate increases if EMAT decreases, whereas multilevel paging will result in a longer EMAT.
• TLB requires only one primary memory access.

Disadvantages

• TLB can only store the data for one process at once.
• TLB performance decreases due to a fewer hit ratio caused by repeated transactions.
• It uses special hardware that's why it is overpriced.