A Real TLB Entry

Finally, let’s briefly look at a real TLB. This example is from the MIPS R4000“MIPS R4000 Microprocessor User’s Manual”. by Joe Heinrich. Prentice-Hall, June 1993. Available: http://cag.csail.mit.edu/raw/ . documents/R4400 Uman book Ed2.pdf A manual, one that is surprisingly readable. Or is it?, a modern system that uses software-managed TLBs; a slightly simplified MIPS TLB entry can be seen in the figure below.

The MIPS R4000 supports a 32-bit address space with 4KB pages. Thus, we would expect a 20-bit VPN and 12-bit offset in our typical virtual address. However, as you can see in the TLB, there are only 19 bits for the VPN; as it turns out, user addresses will only come from half the address space (the rest reserved for the kernel) and hence only 19 bits of VPN are needed. The VPN translates to up to a 24-bit physical frame number (PFN) and hence can support systems with up to 64GB of (physical) main memory (${}^{}$ ...