Who Handles The TLB Miss?
Understand the mechanisms behind handling TLB misses, comparing hardware-managed TLBs in CISC systems with software-managed TLBs in RISC architectures. Learn how operating systems respond to TLB misses, the role of trap handlers, and key differences between valid bits in TLBs and page tables, enabling you to grasp efficient virtual memory management.
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One question that we must answer: who handles a TLB miss? Two answers are possible: the hardware, or the software (OS).
Hardware handling TLB miss
In the olden days, the hardware had complex instruction sets (sometimes called CISC, for complex-instruction set computers) and the people who built the hardware didn’t much trust those sneaky OS people. Thus, the hardware would handle the TLB miss entirely. To do this, the hardware has to know exactly where the page tables are located in memory (via a page-table base register, used in Line 11 in the code snippet captioned TLB Control Flow Algorithm), as well as their exact format; on a miss, the hardware would “walk” the page table, find the correct page-table entry and extract the desired translation, update the TLB with the translation, and retry the instruction. An example of an “older” architecture that has hardware-managed TLBs is the Intel x86 architecture, which uses a fixed multi-level page table (see the next chapter for details);
Software-managed TLB
More modern architectures (e.g.,